PACT 2007 Accepted Posters
The following posters have been accepted for presentation at PACT 2007.
Ring Prediction for Non-Uniform Cache Architectures
Sayaka Akioka, Feihui Li, Padma Raghavan, Mahmut Kandemir and Mary Jane Irwin
The Pennsylvania State University
Source Level Merging of Independent Programs
Yosi Ben Asher and Moshe Yuda
Haifa University
Studying the impact of synchronization frequency on scheduling tasks with dependencies in heterogeneous systems
Florina Monica Ciorba1, Ioannis Riakiotakis1, Theodore Andronikos2, George Papakonstantinou1 and Anthony T. Chronopoulos3
1National Technical University of Athens,
2Ionian University,
3University of Texas at San Antonio
Fast Prototyping of Complex Signal and Image Processing Applications on SOC using Homogenous
Network of Communicating Processors
Lionel Damez and Jean Pierre Dérutin
Université Blaise Pascal
Stream Scheduling: A Framework to Manage Bulk Operations in a Memory Hierarchy
Abhishek Das and William J. Dally
Stanford University
Studying Compiler Optimizations on Superscalar Processors through Interval Analysis
Stijn Eyerman1, Lieven Eeckhout1 and James E. Smith2
1Ghent University,
2University of Wisconsin-Madison
FastForward for Efficient Pipeline Parallelism
John Giacomoni, Tipp Moseley and Manish Vachharajani
University of Colorado at Boulder
The Automatic Transformation of Linked List Data Structures
Sven Groot, Harmen L.A. van der Spek, Erwin M. Bakker and Harry A.G. Wijshoff
Leiden University
Trace-based Automatic Padding for Locality Improvement with Correlative Data Visualization Interface
Marco Hoebbel, Thomas Rauber and Carsten Scholtes
University of Bayreuth
A New Parallel Gauss-Seidel Method by Iteration Space Alternate Tiling
Changjun Hu, Jilin Zhang, Jue Wang, Jianjiang Li and Liang Ding
University of Science and Technology Beijing
Performance Portable Optimizations for Loops Containing Communication Operations
Costin Iancu1, Wei Chen2 and Katherine Yelick1,2
1LBNL,
2UC Berkeley
Exploring the Application Behavior Space Using Parameterized Synthetic Benchmarks
Ajay Joshi1, Lieven Eeckhout2 and Lizy John1
1University of Texas, Austin,
2Ghent University
Studying Asynchronous Shared Memory Computations
Simo Juvaste
University of Joensuu
Fast Track: Supporting Unsafe Optimizations with Software Speculation
Kirk Kelsey, Chengliang Zhang and Chen Ding
University of Rochester
Hybrid Specialization : A Trade-off Between Static and Dynamic Specialization
Minhaj Ahmad Khan, Henri-Pierre Charles and Denis Barthou
University of Versailles
Rate-Driven Control of Resizable Caches for Highly Threaded SMT Processors
Sonia Lopez1, Steven Dropsho2, David Albonesi3, Oscar Garnica1 and Juan Lanchares1
1Universidad Complutense de Madrid,
2EPFL,
3Cornell University
Redesigning Parallel Symbolic Computations Packages
Georgiana Macariu1, Marc Frincu1, Alexandru Carstea1, Dana Petcu2 and Andrei Eckstein2
1Institute e-Austria Timisoara
2Western University of Timisoara
MLP-Aware Dynamic Cache Partitioning
Miquel Moretó1, Francisco J. Cazorla2, Alex Ramirez1,2 and Mateo Valero1,2
1Universitat Politècnica de Catalunya,
2Barcelona Supercomputing Center
A Lightweight Model for Software Thread-Level Speculation (TLS)
Cosmin E. Oancea and Alan Mycroft
Cambridge University
HelperCoreDB: Exploiting Multicore Technology for Databases
Kostas Papadopoulos, Kyriakos Stavrou and Pedro Trancoso
University of Cyprus
Data Structure Exploration of Dynamic Applications
Lazaros Papadopoulos1,
Christos Baloukas1,
Dimitrios Soudris1,
Konstantinos Potamianos2
and Nikolaos Voros2
1Democritus University of Thrace,
2Intracom Telecom Solutions
Dynamic Cache Placement with Two-level Mapping to Reduce Conflict Misses
Kaushik Rajan, R. Govindarajan and Bharadwaj Amrutur
Indian Institute of Science, Bangalore
Runahead Threads: Reducing Resource Contention in SMT Processors
Tanausu Ramirez1, Oliverio Santana2, Alex Pajuelo1 and Mateo Valero1,3
1Universitat Politècnica de Catalunya,
2Universidad de Las Palmas de Gran Canaria,
3Barcelona Supercomputing Center
Reducing the Impact of Process Variability with Prefetching and Criticality-Based Resource Allocation
Bogdan Romanescu, Michael Bauer, Daniel Sorin and Sule Ozev
Duke University
Drug Design on the Cell Broadband Engine
Harald Servat1, Cecilia Gonzalez-Alvarez2, Xavier Aguilar1, Daniel Cabrera-Benitez2 and Daniel Jimenez-Gonzalez2
1Barcelona Supercomputing Center,
2Universitat Politècnica de Catalunya
Bridging Inputs and Program Dynamic Behavior
Xipeng Shen and Feng Mao
The College of William and Mary
Power-Aware Compiler Controllable Chip Multiprocessor
Hiroaki Shikano1,2, Jun Shirako1, Yasutaka Wada1, Keiji Kimura1, and Hironori Kasahara1
1Waseda University,
2Hitachi, Ltd.
RSTM : A Relaxed Consistency Software Transactional Memory on Multicores
Jaswanth Sreeram, Romain Cledat, Tushar Kumar and Santosh Pande
Georgia Institute of Technology
VB-MT: Design Issues and Performance of the Validation Buffer Microarchitecture for Multithreaded Processors
Rafael Ubal, Julio Sahuquillo, Salvador Petit, Pedro López and Jose Duato
Universidad Politècnica de Valencia
A Scalable Low Power Store Queue For Large Instruction Window Superscalar processors
Rajesh Vivekanandham and R. Govindarajan
Indian Institute of Science, Bangalore
Adapting to Intermittent Faults in Future Multicore Systems
Philip Wells, Koushik Chakraborty and Gurindar Sohi
University of Wisconsin-Madison
A Phase-Adaptive Approach to Increasing Cache Performance
Matthew Watkins1, Lambert Schaelicke2 and Sally McKee1
1Cornell University,
2Intel Corporation
Compiler Optimizations for Fault Tolerance Software Checking
Jing Yu and María Jesús Garzarán
University of Illinois at Urbana-Champaign
Optimizing Bandwidth Constraint through Register Interconnection
for Stream Processors
Weihua Zhang, Tao Bao, Binyu Zang and Chuanqi Zhu
Fudan University
