PACT-2011
Galveston Island, Texas, USA
October 10-14, 2011

The Twentieth International Conference on
Parallel Architectures and Compilation Techniques (PACT)
Galveston Island, Texas, USA
October 10-14, 2011

PACT 2011 Posters

A Hierarchical Apporach to Maximizing MapReduce Efficiency

Zhiwei Xiao (Fudan Univ), Haibo Chen (Fudan Univ), Binyu Zang (Fudan Univ), and Bo Huang (Intel, China)

Building Retargetable and Efficient Compilers for Multimedia Instruction Sets

Serge Guelton (Telecom Bretagne), Adrien Guinet (Telecom Bretagne), and Ronan Keryell (HPC Project)

Compiler Directed Data Locality Optimization for Multicore Achitectures

Wei Ding (Penn State Univ), Jithendra Srinivas (Penn State Univ), Mahmut Kandemir (Penn State Univ), and Mustafa Karakoy (Imperial College)

CriticalFacult: Amplifying Soft Error Effect Using Vulnerability-Driven Injection

Xin Xu (George Washington Univ) and Manlap Li (George Washington Univ)

Understanding the Behavior of Pthread Applications on Non-Uniform Cache Architectures

Gagandeep S. Sachdev (Univ of Utah), Kshitij Sudan (Univ of Utah), Mary W. Hall (Univ of Utah), and Rajeev Balasubramonian (Univ of Utah)

Exploiting Mutual Awareness between Prefetchers and On-chip Networks in Multi-cores

Junghoon Lee (KAIST), Minjeong Shin (KAIST), Hanjoon Kim (KAIST), John Kim (KAIST), and Jaehyuk Huh (KAIST)

Decoupled Architecture as a Low-Complexity Alternative to Out-of-order Execution

Neal Crago (UIUC) and Sanjay Patel (UIUC)

MCFQ: Leveraging Memory-level Parallelism and Application's Cache Friendliness for Efficient Management of Quasi-partitioned Last-level Cache

Dimitris Kaseridis (UT Austin), Muhammad Faisal Iqbal (UT Austin), Jeffrey Stuecheli (UT Austin), Lizy Kurian John (UT Austin)

MRAC: A Memristor-based Reconfigurable Framework for Adaptive Cache Replacement

Ping Zhou (Univ of Pittsburgh), Bo Zhao (Univ of Pittsburgh), Youtao Zhang (Univ of Pittsburgh), Jun Yang, (Univ of Pittsburgh) and Yiran Chen (Univ of Pittsburgh)

Parameterized Micro-benchmarking: An Auto-tuning Approach for Complex Applications

Wejing Ma (Ohio State Univ), Sriram Krishnamoorthy (Pacific Northwest National Lab), and Gagan Agrawal (Ohio State Univ)

Prediction Based DRAM Row-Buffer Management in the Many-Core Era

Manu Awasthi (Univ of Utah), David Nellans (Univ of Utah), Moinuddin K. Qureshi (IBM), and Rajeev Balasubramonian (Univ of Utah), and Al David (Univ of Utah)

Program Interferometry

Zhe Wang (UT San Antonio) and Daniel A. Jimenez (UT San Antonio)

Regulating Locality vs. Parallelism Tradeoffs in Multiple Memory Controller Environments

Syed Minhaj Hassan (Georgia Tech), Dhruv Choudhary (Georgia Tech), Mitchelle Rasquinha (Georgia Tech), and Sudhakar Yalamanchili (Georgia Tech)

Row-Buffer Reorganization: Simultaneously Improving Performance and Reducing Energy in DRAMs

Nagendra Gulur (TI), R. Manikantan (Indian Institute of Science), Mahesh Mehendale (TI), and R. Govindarajan (Indian Institute of Science)

Scalable Proximity-Aware Cache Replication in Chip Multiprocessors

Chongmin Li (IBM Austin), Haixia Wang (IBM Austin), Yibo Xue (IBM Austin), Dongsheng Wang (Tsinghua Univ), and Jian Li (IBM Austin)

Scalable and Efficient Bounds Checking for Large-Scale CMP Environments

Baik Song An (Texas A&M), Ki Hwan Yum (Texas A&M), and Eun Jung Kim (Texas A&M)

An Alternative Memory Access Scheduling in Manycore Accelerators

Yonggon Kim (KAIST), Hyunseok Lee (KAIST), and John Kim (KAIST)

Beforehand Migration on D-NUCA Caches

Javier Lira (Univ Politecnica de Catalunya), Timothy M. Jones (Unif of Cambridge), Carlos Molina (Univ Rovira i Virgili), and Antonio Gonzalez (Intel Barcelona Research Center, Intel Labs - UPC)

SymptomTM: Symptom-Based Error Detection and Recovery Using Hardware Transactional Memory

Gulay Yalcin (Barcelona Supercomputing Center), Osman Unsal (Barcelona Supercomputing Center), Adrian Cristal (Barcelona Supercomputing Center), Ibrahim Hur (Barcelona Supercomputing Center), and Mateo Valero (Barcelona Supercomputing Center)

rPRAM: Exploring Redundancy Techniques to Improve Lifetime of PCM-based Main Memory

Jie Chen (George Washington Univ), Zachary Winter (George Washington Univ), Guru Venkataramani (George Washington Univ), and H. Howie Huang (George Washington Univ)

Pi-TM: Pessimistic Invalidation for Scalable Lazy Hardware Transactional Memory

Anurag Negi (Chalmers Univ of Tech, Sweden), Ruben Titos-Gil (Univ de Murcia, Spain), Manuel E. Acacio (Univ de Murcia, Spain), Jose M. Garcia (Univ de Murcia, Spain), and Per Stenstrom (Chalmers Univ of Tech, Sweden)