PACT 2011: Program

International Conference on 
Parallel Architecture and Compilation Techniques
Galveston Island, Texas, USA
October 10-14, 2011

The Twentieth International Conference on
Parallel Architectures and Compilation Techniques (PACT)
Galveston Island, Texas, USA
October 10-14, 2011

PACT 2011 Program

The PACT 2011 tutorials and workshops will be held Monday October 10 and Friday October 14 - see the Tutorials and Workshops Schedule for details. The PACT 2011 technical sessions will be held Tuesday October 11 through Thursday October 13 at the conference hotel, the Hotel Galvez.

PACT 2011 Program - Monday, October 10, 2011
17:30-19:30 Welcome Reception (Hotel Galvez Pool Area)
PACT 2011 Program - Tuesday, October 11, 2011
8:00-9:00 Continental Breakfast (Veranda)
8:45-9:00 Opening Remarks (Music Hall)
Lawrence Rauchwerger, General Chair
Vivek Sarkar, Program Chair
9:00-10:00 Session 1: Keynote (Music Hall)
Stuart Feldman, Computing at the Extremes
Session Chair: Kemal Ebcioglu
10:00-10:30 Break (Peacock Alley)
10:30-12:00 Session 2a: Coherence (Music Hall)
Session Chair: John Cavazos

SPATL: Honey, I Shrunk the Coherence Directory
Hongzhou Zhao (U. Rochester), Arrvindh Shriraman (Simon Fraser), Sandhya Dwarkadas (U. Rochester), and Vijayalakshmi Srinivasan (IBM Research)
POPS: Coherence Protocol Optimization for Both Private and Shared Data
Hemayet Hossain (U. Rochester), Sandhya Dwarkadas (U. Rochester), and Michael C. Huang (U. Rochester)
An OpenCL Framework for Homogeneous Manycores with No Hardware Cache Coherence
Jun Lee (Seoul National U.), Jungwon Kim (Seoul National U.), Junghyun Kim (Seoul National U.), Sangmin Seo (Seoul National U.), and Jaejin Lee (Seoul National U.)

  Session 2b: Scheduling (Terrace Ballroom)
Session Chair: Pen Yew

A Unified Scheduler for Recursive and Task Dataflow Parallelism
Hans Vandierendonck (UGent, FORTH-ICS), George Tzenakis (FORTH-ICS), and Dimitrios S. Nikolopoulos (FORTH-ICS)
No More Backstabbing... A Faithful Scheduling Policy for Multithreaded Programs
Kishore Kumar Pusukuri (UC Riverside), Rajiv Gupta (UC Riverside), and Laxmi N. Bhuyan (UC Riverside)
Dynamic Fine-Grain Scheduling of Pipeline Parallelism
Daniel Sanchez (Stanford), David Lo (Stanford), Richard M. Yoo (Stanford), Jeremy Sugerman (Stanford), and Christos Kozyrakis (Stanford)

12:00-13:30 Lunch (Veranda)
13:30-15:00 Session 3a: High-Level Programming Frameworks (Music Hall)
Session Chair: Zoran Budimlic

Compiling Dynamic Data Structures in Python to Enable the Use of Multi-core and Many-core Libraries
Bin Ren (Ohio State) and Gagan Agrawal (Ohio State)
Efficient Parallel Graph Exploration for Multi-Core CPU and GPU
Sunpgack Hong (Stanford), Tayo Oguntebi (Stanford), and Kunle Olukotun (Stanford)
A Heterogeneous Parallel Framework for Domain-Specific Languages
Kevin J. Brown (Stanford), Arvind K. Sujeeth (Stanford), and HyoukJoong Lee (Stanford), Tiark Rompf (EPFL), and Hassan Chafi (Stanford) and Kunle Olukotun (Stanford)

  Session 3b: Power Efficiency (Terrace Ballroom)
Session Chair: Kei Hiraki

PEPSC: A Power-Efficient Processor for Scientific Computing
Ganesh Dasika (U. Michigan), Ankit Sethia (U. Michigan), Trevor Mudge (U. Michigan), and Scott Mahlke (U. Michigan)
Improving Throughput of Power-Constrained GPUs Using Dynamic Voltage/Frequency and Core Scaling
Jungseob Lee (U. Wisconsin-Madison), Vijay Satish (U. Wisconsin-Madison), Katherine Compton (U. of Wisconsin-Madison), Mike Schulte (AMD), and Nam Kim (U. of Wisconsin-Madison)
Performance per Watt Benefits of Dynamic Core Morphing in Asymmetric Multicores
Rance Rodrigues (U. Massachusetts at Amherst), Arunachalam Annamalai (U. Massachusetts at Amherst), Israel Koren (U. Massachusetts at Amherst), Sandip Kundu (U. Massachusetts at Amherst) and Omer Khan (U. Massachusetts at Lowell)

15:00-15:30 Break (Peacock Alley)
15:30-17:00 Session 4: Best Paper Session (Music Hall)
Session Chair: Vivek Sarkar

Phased-Based Application-Driven Hierarchical Power Management on the Single-chip Cloud Computer
Nikolas Ioannou (University of Edinburgh), Matthias Gries (Intel, Braunschweig, Germany), Michael Kauschke (Intel, Braunschweig, Germany), and Marcelo Cintra (University of Edinburgh)
Optimizing Data Layouts for Parallel Computation on Multicores
Yuanrui Zhang (Penn State), Wei Ding (Penn State), Jun Liu (Penn State), and Mahmut Kandemir (Penn State)
DeNovo: Rethinking the Memory Hierarchy for Disciplined Parallelism
Byn Choi (UIUC), Rakesh Komuravelli (UIUC), Hyojin Sung (UIUC), Robert Smolinski (UIUC), Nima Honarmand (UIUC), Sarita V. Adve (UIUC), Vikram S. Adve (UIUC), Nicholas P. Carter (Intel) and Ching-Tsun Chou (Intel)

17:00-20:00 Poster Session and Reception (Terrace Ballroom and Peacock Alley)
PACT Poster Listing
ACM SRC Poster Listing
PACT 2011 Program - Wednesday, October 12, 2011
8:00-9:00 Continental Breakfast (Veranda)
9:00-10:00 Session 5: Keynote (Music Hall)
Leslie Valiant, Do Parallel Algorithms and Programs Need to be Parameter Aware?
Session Chair: Lawrence Rauchwerger
10:00-10:30 Break (Peacock Alley)
10:30-12:00 Session 6a: ACM Student Research Competition Presentations (Music Hall)
Session Chair: Chen Ding

ACM SRC Poster Listing

  Session 6b: Transactional Memory (Terrace Ballroom)
Session Chair: Mikel Lujan

STM2: A Parallel STM for High Performance Simultaneous Multithreading Systems
Gokcen Kestor (Barcelona Supercomputing Center), Roberto Gioiosa (Barcelona Supercomputing Center), Tim Harris (Microsoft Research), Osman Unsal (Barcelona Supercomputing Center), Adrian Cristal (Barcelona Supercomputing Center), Ibrahim Hur (Barcelona Supercomputing Center), and Mateo Valero (Univesitat Politecnica de Catalunya)
Making STMs Cache Friendly with Compiler Transformations
Sandya Mannarswamy (Indian Institute of science, Bangalore & Hewlett Packard) and Ramaswamy Govindarajan (Indian Institute of Science, Bangalore)

12:00-13:00 Lunch (Veranda)
13:00 Conference Excursion to NASA - Sponsored by Intel
19:00 Conference Banquet (The Tremont House Ballroom)  - Sponsored by Samsung
PACT 2011 Program - Thursday October 13, 2011
8:00-9:00 Continental Breakfast (Veranda)
9:00-10:00 Session 7: Keynote (Music Hall)
Shekhar Borkar, The Exascale Challenge (slides)
Session Chair: Vivek Sarkar
10:00-10:30 Break (Peacock Alley)
10:30-12:00 Session 8a: Customized Processors (Music Hall)
Session Chair: Richard Schooler

StVEC: A Vector Instruction Extension for High Performance Stencil Computation
Naser Sedaghati (Ohio State), Renji Thomas (Ohio State), Louis-Noel Pouchet (Ohio State), Radu Teodorescu (Ohio State), and P Sadayappan (Ohio State)
OpenMDSP: Extending OpenMP to Program Multi-Core DSP
Jiangzhou He (Tsinghua U), Wenguang Chen (Tsinghua U.), Guangri Chen (Huawei Technologies Co. Ltd.), Weimin Zheng (Tsinghua U.), Zhizhong Tang (Tsinghua U.), and Handong Ye (Huawei Technologies Co. Ltd.)
ARIADNE: Agnostic Reconfiguration In A Disconnected Network Environment
Konstantinos Aisopos (Princeton), Andrew DeOrio (U. Michigan), Li-Shiuan Peh (MIT), and Valeria Bertacco (U. Michigan)

  Session 8b: Locality (Terrace Ballroom)
Session Chair: Raj Barik

Enhancing Data Locality for Dynamic Simulations through Asynchronous Data Transformations and Adaptive Control
Bo Wu (The College of William and Mary), Eddy Z. Zhang (The College of William and Mary), and Xipeng Shen (The College of William and Mary)
SFMalloc: A Lock-Free and Mostly Synchronization-Free Dynamic Memory Allocator for Manycores
Sangmin Seo (Seoul National University), Junghyun Kim (Seoul National University), and Jaejin Lee (Seoul National University)
Coherent Profiles: Enabling Efficient Reuse Distance Analysis of Multicore Scaling for Loop-based Parallel Programs
Meng-Ju Wu (U. Maryland at College Park) and Donald Yeung (U. of Maryland at College Park)

12:00-13:30 Lunch (Veranda)
13:30-15:00 Session 9a: Memory Hierarchies (Music Hall)
Session Chair: Jaejin Lee

DiDi: Mitigating The Performance Impact of TLB Shootdowns Using A Shared TLB Directory
Carlos Villavieja (UPC,BSC), Vasilis Karakostas (BSC), Lluis Vilanova (UPC,BSC), Yoav Etsion (BSC), Alex Ramirez (UPC, BSC), Avi Mendelson (Microsoft), Nacho Navarro (UPC, BSC) Adrian Cristal (BSC) and Osman Unsal (BSC)
Linear-time Modeling of Program Working Set in Shared Cache
Xiaoya Xiang (U. Rochester), Bin Bao (U. Rochester), Chen Ding (U. Rochester) and Yaoqing Gao (IBM Toronto)
Using a Reconfigurable L1 Data Cache for Efficient Version Management in Hardware Transactional Memory
Adria Armejach (BSC, UPC) and Azam Seyedi (BSC, UPC), Ruben Titos (U. de Murcia), Ibrahim Hur (BSC), Osman S. Unsal (BSC), and Adrian Cristal (BSC), and Mateo Valero (BSC, UPC)

  Session 9b: SPMD Analysis (Terrace Ballroom)
Session Chair: Reid Tatge

Correctly Treating Synchronizations in Compiling Fine-Grained SPMD-Threaded Programs for CPU
Ziyu Guo (The College of William and Mary), Eddy Z. Zhang (The College of William and Mary), and Xipeng Shen (The College of William and Mary)
Divergence Analysis and Optimizations
Bruno Rocha Coutinho (UFMG), Diogo Nunes Sampaio (UFMG), Fernando Magno Quintao Pereira (UFMG), and Wagner Meira Jr. (UFMG)
Large Scale Verification of MPI Programs Using Lamport Clocks with Lazy Update
Anh Vo (Utah), Ganesh Gopalakrishnan (Utah), and Robert M. Kirby (Utah) and Bronis R. de Supinski (LLNL), Martin Schulz (LLNL)`, and Greg Bronevetsky (LLNL)

15:00-15:30 Break (Peacock Alley)
15:30-17:00 Session 10a: Compiler Optimizations (Music Hall)
Session Chair: Francois Irigoin

An Evaluation of Vectorizing Compilers
Saeed Maleki (UIUC), David Padua (UIUC), and Maria J. Garzaran (UIUC) Yaoqing Gao (IBM Toronto Laboratory) and Tommy Wong (IBM Toronto Laboratory)
Modeling and Performance Evaluation of TSO-Preserving Binary Optimization
Cheng Wang (Intel Labs) and Youfeng Wu (Intel Labs)
Exploiting Task Order Information for Optimizing Sequentially Consistent Java Programs
Christoph M. Angerer (ETH Zurich) and Thomas R. Gross (ETH Zurich)

  Session 10b: Potpourri (Terrace Ballroom)
Session Chair: Nancy Amato

Memory Architecture for Integrating Emerging Memory Technologies
Kun Fang (UIC), Long Chen (Iowa State), Zhao Zhang (Iowa State), and Zhichun Zhu (UIC)
Speculative Parallelization in Decoupled Look-ahead
Alok Garg (U. Rochester), Raj Parihar (U. Rochester), and Michael C. Huang (U. Rochester)
Optimizing Regular Expression Matching with SR-NFA on Multi-Core Systems
Yi-Hua Edward Yang (USC) and Viktor K. Prasanna (USC)

17:00 Conference Closing (Music Hall)
17:30 Dinner Excursion to Moody Gardens Aquarium