Search Space Properties for
Mapping Pipelined FPGA
Applications
Heidi Ziegler, Mary Hall, Byoungro So
To appear at
16th Workshop on Languages and Compilers for Parallel Computing (LCPC03), College Station, TX, 2-4 October 2003
Full Text, Printable Abstract.
Abstract
This paper describes an automated approach to hardware design
space exploration, through a collaboration between parallelizing
compiler technology and high-level synthesis tools. In previous
work, we described a compiler algorithm that optimizes individual
loop nests, expressed in C, to derive an efficient FPGA
implementation. In this paper, we describe a global optimization
strategy that maps multiple loop nests to a pipelined FPGA
implementation. The global optimization algorithm automatically
transforms the computation to incorporate explicit communication
and data reorganization between pipeline stages, and uses metrics
to guide design space exploration to consider the impact of
communication and to achieve balance between producer and consumer
data rates across pipeline stages. In a case study with a machine
vision application, we find that on-chip communication greatly
reduces the number of memory accesses, and thus results in designs
that are less memory bound.